PCIe 6.0: Testing for a New Generation

Tackling verification challenges for PCIe Gen5
With the PCIe Gen5 interface standard for connecting high-speed components, engineers gain a 32 GT/s data rate per lane, doubling speed over the prior generation, and new features such as support for alternate protocols. But there are also challenges. This white paper details them as well as new features – and provides a case study on how Anritsu used a Siemens Verification IP solution to offer Gen 5 support for a 5G/IoT signal quality analyzer. What you’ll gain from reading this paper: Benefits of PCIe 5.0 once challenges are met Gen 5 tips for verification engineers Need-to-know details for verification engineering How a test and measurement equipment maker upgraded

PCIe 6.0: Testing for a New Generation
PCIe 6.0 is the next-generation computer bus technology for high-speed devices for computer drives, graphics cards, Wi-Fi routers, and internal Ethernet connections. This white paper, “PCIe 6.0: Testing for a New Generation,” outlines the enhanced PCIe 6.0 technologies, such as PAM4, Forward Error Correction (FEC) and link equalization. This white paper will improve your understanding of: Data rate details for each generation of the standard since Compliance requirements and metrics for making the upgrade Need-to-know facts on PAM4, BER, FEC, Link equalization, and JTOL Guidelines for selecting a test system to verify new designs