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Applying IBIS-AMI Techniques to DDR5 Analysis
DDR5 memory is slated to run at speeds from 3200 MT/s to 6400 MT/s. These speeds are well into the range where Tx/Rx equalization is used to ensure reliable signal transmission in serial channel applications. DDR5 is expected to make use of the same techniques (FIR, CTLE, DFE) to improve signal quality when the final DDR5 specification is published. While DDR5 signaling speeds have reached traditional SerDes speeds, there are significant differences between DDR and serial channel applications, including: Shorter lower loss channels with more discontinuities and reflections Multiple driver / receiver combinations Multiple signal terminations Single-ended signaling Variable network topologies (DIMMs present or absent) Short transmission bursts followed by network I/O reconfiguration Bi-directional signaling At first, application of SerDes equalization techniques and AMI models seems like an obvious approach to improving DDR5 signal quality. A closer inspection reveals that the design problems incurred by DDR5 topologies are quite different than the signaling challenges that SerDes equalization techniques were originally designed to overcome. However, thoughtful application of AMI models and AMI simulation techniques can highlight which DDR5 signal quality issues are significant and what techniques can best be used to overcome them. This paper looks at the challenges of achieving reliable data transmission for a DDR5 data net operating at a variety of speeds. We discuss how AMI-style analysis can be used to identify which data transfers are the limiting factors in high speed performance and what equalization / modeling techniques can be used to address them.
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